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FT232R USB UART IC DatasheetVersion 2.16Document No.: FT 000053 Clearance No.: FTDI# 38Pin No.NameType2025VCCAGNDPWRPWRPin No.8, 8OSCOOutputPin scriptionthis pin to power external logic if required. This pin can also be used tosupply the VCCIO pin. 3.3V to 5.25V supply to the device core. (see Note 1)Device analogue ground supply for internal clock multiplierTable 3.2 Power and Ground GroupDescriptionNo internal connectionActive low reset pin. This can be used by an external device to reset theFT232R. If not required can be left unconnected, or pulled up to VCC.Puts the device into IC test mode. Must be tied to GND for normaloperation, otherwise the device will appear to fail.Input 12MHz Oscillator Cell. Optional – Can be left unconnected fornormal operation. (see Note 2)Output from 12MHZ Oscillator Cell. Optional – Can be left unconnectedfor normal operation if internal Oscillator is used. (see Note 2)Table 3.3 Miscellaneous Signal GroupDescriptionTransmit Asynchronous Data Output.Data Terminal Ready Control Output / Handshake Signal.Request to Send Control Output / Handshake Signal.Receiving Asynchronous Data Input.Ring Indicator Control Input. When remote wake up is enabled in theinternal EEPROM taking RI# low (20ms active low pulse) can be used toresume the PC USB host controller from suspend.Data Set Ready Control Input / Handshake Signal.Data Carrier Detect Control Input.Clear To Send Control Input / Handshake Signal.Configurable CBUS output only Pin. Function of this pin is configured inthe device internal EEPROM. Factory default configuration is SLEEP#. SeeCBUS Signal Options, Table 3.9.Configurable CBUS I/O Pin. Function of this pin is configured in thedevice internal EEPROM. Factory default configuration is TXDEN. SeeCBUS Signal Options, Table 3.9.Configurable CBUS I/O Pin. Function of this pin is configured in thedevice internal EEPROM. Factory default configuration is PWREN#. SeeCBUS Signal Options, Table 3.9. PWREN# should be used with a 10kΩresistor pull up.Configurable CBUS I/O Pin. Function of this pin is configured in thedevice internal EEPROM. Factory default configuration is RXLED#. SeeCBUS Signal Options, Table 3.9.Configurable CBUS I/O Pin. Function of this pin is configured in thedevice internal EEPROM. Factory default configuration is TXLED#. SeeCBUS Signal Options, Table 3.9.3.4 UART Interface and CUSB Group (see note 3)Notes:1. The minimum operating voltage VCC must be 4.0V (could use VBUS 5V) when using theinternal clock generator. Operation at 3.3V is possible using an external crystal oscillator.2. For details on how to use an external crystal, ceramic resonator, or oscillator with the FT232R,please refer Section 7.63. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ resistors. Thesepins can be programmed to gently pull low during USB suspend (PWREN# “1”) by setting anoption in the internal EEPROM.Copyright Future Technology Devices International Limited8

FT232R USB UART IC DatasheetVersion 2.16Document No.: FT 000053 Clearance No.: FTDI# 383.3 QFN-32 PackageFigure 3.2 QFN-32 Package Pin Out and schematic symbol3.4 QFN-32 Package Signal DescriptionNameType14USBDPI/O15USBDMI/OPin No.NamePin No.14, 17,2016DescriptionUSB Data Signal Plus, incorporating internal series resistor and 1.5kΩ pullup resistor to 3.3V.USB Data Signal Minus, incorporating internal series resistor.Table 3.5 USB Interface GroupTypeDescriptionVCCIOPWR 1.8V to 5.25V supply for the UART Interface and CBUS group pins (2,3,6,7,8,9,10,11,21,22,30,31,32). In USB bus powered designs connect thispin to 3V3OUT to drive out at 3.3V levels, or connect to VCC to drive outat 5V CMOS level. This pin can also be supplied with an external 1.8Vto 2.8V supply in order to drive out at lower levels. It should be notedthat in this case this supply should originate from the same source as thesupply to VCC. This means that in bus powered designs a regulator whichis supplied by the 5V on the USB bus should be used.GNDPWRDevice ground supply pins.3V3OUTOutput 3.3V output from integrated LDO regulator. This pin should be decoupledCopyright Future Technology Devices International Limited9

FT232R USB UART IC DatasheetVersion 2.16Document No.: FT 000053 Clearance No.: FTDI# 38Pin No.NameType1924VCCAGNDPWRPWRPin No.NameType5, 12,13, 23,25, putPin US410CBUS211CBUS321CBUS122CBUS0Descriptionto ground using a 100nF capacitor. The purpose of this output is to providethe internal 3.3V supply to the USB transceiver cell and the internal1.5kΩ pull up resistor on USBDP. Up to 50mA can be drawn from this pinto power external logic if required. This pin can also be used to supply theVCCIO pin. 3.3V to 5.25V supply to the device core. (See Note 1).Device analogue ground supply for internal clock multiplier.Table 3.6 Power and Ground GroupDescriptionNo internal connection. Do not connect.Active low reset. Can be used by an external device to reset the FT232R. Ifnot required can be left unconnected, or pulled up to VCC.Puts the device into IC test mode. Must be tied to GND for normaloperation, otherwise the device will appear to fail.Input 12MHz Oscillator Cell. Optional – Can be left unconnected for normaloperation. (See Note 2).Output from 12MHZ Oscillator Cell. Optional – Can be left unconnected fornormal operation if internal Oscillator is used. (See Note 2).Table 3.7 Miscellaneous Signal t Asynchronous Data Output.Data Terminal Ready Control Output / Handshake Signal.Request to Send Control Output / Handshake Signal.Receiving Asynchronous Data Input.Ring Indicator Control Input. When remote wake up is enabled in the internalInputEEPROM taking RI# low (20ms active low pulse) can be used to resume thePC USB host controller from suspend.InputData Set Ready Control Input / Handshake Signal.InputData Carrier Detect Control Input.InputClear To Send Control Input / Handshake Signal.Configurable CBUS output only Pin. Function of this pin is configured in theI/Odevice internal EEPROM. Factory default configuration is SLEEP#. See CBUSSignal Options, Table 3.9.Configurable CBUS I/O Pin. Function of this pin is configured in the deviceI/Ointernal EEPROM. Factory default configuration is TXDEN. See CBUS SignalOptions, Table 3.9.Configurable CBUS I/O Pin. Function of this pin is configured in the deviceI/Ointernal EEPROM. Factory default configuration is PWREN#. See CBUS SignalOptions, Table 3.9. PWREN# should be used with a 10kΩ resistor pull up.Configurable CBUS I/O Pin. Function of this pin is configured in the deviceI/Ointernal EEPROM. Factory default configuration is RXLED#. See CBUS SignalOptions, Table 3.9.Configurable CBUS I/O Pin. Function of this pin is configured in the deviceI/Ointernal EEPROM. Factory default configuration is TXLED#. See CBUS SignalOptions, Table 3.9.Table 3.8 UART Interface and CBUS Group (see note 3)Notes:1. The minimum operating voltage VCC must be 4.0V (could use VBUS 5V) when using theinternal clock generator. Operation at 3.3V is possible using an external crystal oscillator.2. For details on how to use an external crystal, ceramic resonator, or oscillator with the FT232R,please refer to Section 7.6.Copyright Future Technology Devices International Limited10

FT232R USB UART IC DatasheetVersion 2.16Document No.: FT 000053 Clearance No.: FTDI# 383. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ resistors. Thesepins can be programmed to gently pull low during USB suspend (PWREN# “1”) by setting anoption in the internal EEPROM.3.5 CBUS Signal OptionsThe following options can be configured on the CBUS I/O pins. CBUS signal options are common to bothpackage versions of the FT232R. These options can be configured in the internal EEPROM using thesoftware utility FT PROG, which can be downloaded from the FTDI Utilities (www.ftdichip.com). Thedefault configuration is described in Section 8.CBUS SignalOptionAvailable On CBUS PinTXDENCBUS0, CBUS1, CBUS2,CBUS3, CBUS4PWREN#CBUS0, CBUS1, CBUS2,CBUS3, CBUS4TXLED#CBUS0, CBUS1, CBUS2,CBUS3, CBUS4RXLED#CBUS0, CBUS1, CBUS2,CBUS3, CBUS4TX&RXLED#CBUS0, CBUS1, CBUS2,CBUS3, CBUS4SLEEP#CBUS0, CBUS1, CBUS2,CBUS3, ngRDnCBUS0, CBUS1, CBUS2,CBUS3, CBUS4CBUS0, CBUS1, CBUS2,CBUS3, CBUS4CBUS0, CBUS1, CBUS2,CBUS3, CBUS4CBUS0, CBUS1, CBUS2,CBUS3, CBUS4DescriptionEnable transmit data for RS485Output is low after the device has been configuredby USB, then high during USB suspending mode.This output can be used to control power toexternal logic P-Channel logic level MOSFET switch.Enable the interface pull-down option when usingthe PWREN# in this way.*Transmit data LED drive: Data from USB Host toFT232R. Pulses low when transmitting data via USB.See Section 7.5 for more details.Receive data LED drive: Data from FT232R to USBHost. Pulses low when receiving data via USB. SeeSection 7.5 for more details.LED drive – pulses low when transmitting orreceiving data via USB. See Section 7.5 for moredetails.Goes low during USB suspend mode. Typically usedto power down an external TTL to RS232 levelconverter IC in USB to RS232 converter designs.48MHz 0.7% Clock output. **24 MHz Clock output. **12 MHz Clock output. **6 MHz 0.7% Clock output. **CBUS bit bang mode option. Allows up to 4 of theCBUS pins to be used as general purpose I/O.Configured individually for CBUS0, CBUS1, CBUS2CBUS0, CBUS1, CBUS2,and CBUS3 in the internal EEPROM. A separateCBUS3application note, AN232R-01, available from FTDIwebsite (www.ftdichip.com) describes in more detailhow to use CBUS bit bang mode.Synchronous and asynchronous bit bang mode WR#CBUS0, CBUS1strobe output.CBUS0, CBUS1, CBUS2,Synchronous and asynchronous bit bang mode RD#CBUS3strobe output.Table 3.9 CBUS Configuration Control* PWREN# must be used with a 10kΩ resistor pull up.**When in USB suspend mode the outputs clocks are also suspended.Copyright Future Technology Devices International Limited11

FT232R USB UART IC DatasheetVersion 2.16Document No.: FT 000053 Clearance No.: FTDI# 384Function DescriptionThe FT232R is a USB to serialexternal component count byintegrated clock circuit whichoperate efficiently with a USBavailable.UART interface device which simplifies USB to serial designs and reducesfully integrating an external EEPROM, USB termination resistors and anrequires no external crystal, into the device. It has been designed tohost controller by using as little as possible of the total USB bandwidth4.1 Key FeaturesFunctional Integration. Fully integrated EEPROM, USB termination resistors, clock generation, AVCCfiltering, POR and LDO regulator.Configurable CBUS I/O Pin Options. The fully integrated EEPROM allows configuration of the ControlBus (CBUS) functionality, signal inversion and drive strength selection. There are 5 configurable CBUSI/O pins. These configurable options are 1.2.3.4.5.6.7.TXDEN - transmit enable for RS485 designs.PWREN# - Power control for high power, bus powered designs.TXLED# - for pulsing an LED upon transmission of data.RXLED# - for pulsing an LED upon receiving data.TX&RXLED# - which will pulse an LED upon transmission OR reception of data.SLEEP# - indicates that the device going into USB suspend mode.CLK48 / CLK24 / CLK12 / CLK6 - 48MHz, 24MHz, 12MHz, and 6MHz clock output signaloptions.8. BitBangWRn / BitBangRDn - Synchronous and asynchronous bit bang mode WR# / RD#strobe outputsThe CBUS pins can also be individually configured as GPIO pins, similar to asynchronous bit bang mode.It is possible to use this mode while the UART interface is being used, thus providing up to 4 generalpurpose I/O pins which are available during normal operation. An application note, AN232R-01, availablefrom FTDI website (www.ftdichip.com) describes this feature.The CBUS lines can be configured with any one of these output options by setting bits in the internalEEPROM. The device is supplied with the most commonly used pin definitions pre-programmed - seeSection 8 for details.Asynchronous Bit Bang Mode with RD# and WR# Strobes. The FT232R supports FTDI’s previouschip generation bit-bang mode. In bit-bang mode, the eight UART lines can be switched from the regularinterface mode to an 8-bit general purpose I/O port. Data packets can be sent to the device and they willbe sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud ratepre-scaler). With the FT232R device this mode has been enhanced by outputting the internal RD# andWR# strobes signals which can be used to allow external logic to be clocked by accesses to the bit-bangI/O bus. This option will be described more fully in a separate application note available from FTDIwebsite (www.ftdichip.com).Synchronous Bit Bang Mode. The FT232R supports synchronous bit bang mode. This mode differs fromasynchronous bit bang mode in that the interface pins are only read when the device is written to. Thismakes it easier for the controlling program to measure the response to an output stimulus as the datareturned is synchronous to the output data. An application note, AN232R-01, available from FTDI website(www.ftdichip.com) describes this feature.FTDIChip-ID . The FT232R also includes the new FTDIChip-ID security dongle feature. ThisFTDIChip-ID feature allows a unique number to be burnt into each device during manufacture. Thisnumber cannot be reprogrammed. This number is only readable over USB and forms a basis of a securitydongle which can be used to protect any customer application software being copied. This allows thepossibility of using the FT232R in a dongle for software licensing. Further to this, a renewable licensescheme can be implemented based on the FTDIChip-ID number when encrypted with other information.This encrypted number can be stored in the user area of the FT232R internal EEPROM, and can bedecrypted, then compared with the protected FTDIChip-ID to verify that a license is valid. Web basedCopyright Future Technology Devices International Limited12

FT232R USB UART IC DatasheetVersion 2.16Document No.: FT 000053 Clearance No.: FTDI# 38applications can be used to maintain product licensing this way. An application note, AN232R-02,available from FTDI website (www.ftdichip.com) describes this feature.The FT232R is capable of operating at a voltage supply between 3.3V and 5V with a nominaloperational mode current of 15mA and a nominal USB suspend mode current of 70µA. This allows greatermargin for peripheral designs to meet the USB suspend mode current limit of 2.5mA. An integrated levelconverter within the UART interface allows the FT232R to interface to UART logic running at 1.8V, 2.5V, 3.3V or 5V.4.2 Functional Block DescriptionsThe following paragraphs detail each function within the FT232R. Please refer to the block diagram shownin Figure 2.1.Internal EEPROM. The internal EEPROM in the FT232R is used to store USB Vendor ID (VID), Product ID(PID), device serial number, product description string and various other USB configuration descriptors.The internal EEPROM is also used to configure the CBUS pin functions. The FT232R is supplied with theinternal EEPROM pre-programmed as described in Section 8. A user area of the internal EEPROM isavailable to system designers to allow storing additional data. The internal EEPROM descriptors can beprogrammed in circuit, over USB without any additional voltage requirement. It can be programmedusing the FTDI utility software called FT PROG, which can be downloaded from FTDI Utilities on the FTDIwebsite (www.ftdichip.com). 3.3V LDO Regulator. The 3.3V LDO regulator generates the 3.3V reference voltage for driving theUSB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the3V3OUT regulator output pin. It also provides 3.3V power to the 1.5kΩ internal pull up resistor onUSBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cellsrather than to power external logic. However, it can be used to supply external circuitry requiring a 3.3V nominal supply with a maximum current of 50mA.USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interfaceto the USB cable. The output drivers provide 3.3V level slew rate control signalling, whilst a differentialinput receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USBreset detection conditions respectfully. This function also incorporates the internal USB series terminationresistors on the USB data lines and a 1.5kΩ pull up resistor on USBDP.USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clockand data signals for the Serial Interface Engine (SIE) block.Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock. Thisprovides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the referenceclock for the SIE, USB Protocol Engine and UART FIFO contr

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