1PROBE2.0: A Systematic Framework forRoutability Assessment from Technology to Designin Advanced NodesChung-Kuan Cheng, Fellow, IEEE, Andrew B. Kahng, Fellow, IEEE, Hayoung Kim, Member, IEEE,,Minsoo Kim, Student Member, IEEE, Daeyeal Lee, Student Member, IEEE, Dongwon Park, StudentMember, IEEE, and Mingyu Woo, Student Member, IEEEAbstract—In advanced nodes, scaling of critical dimensionand pitch has not progressed at historical Moore’s Law rates.Thus, scaling boosters are explored to improve achievable power,performance, area and cost (PPAC) in new technologies. However,scaling boosters increase complexity of standard-cell architectures, power delivery, design rules, and other aspects of the designenablement, and may not result in design-level benefits. Therefore, design-technology co-optimization (DTCO) methodologies arerequired to evaluate design-level benefits of scaling boosters. Thekey challenge for DTCO is that large engineering efforts andlong timelines are needed to develop design enablements (e.g.,cell libraries) and perform implementation studies in order toassess technology options.We describe a new framework that can systematically evaluatea measure of intrinsic routability, Kth , across both technologyand design choices. We focus on routability since it is a criticalfactor in the scaling of area and cost. Our framework includesrealistic standard-cell libraries that are automatically generatedusing satisfiability modulo theory (SMT) methods, and a new pinshape selection method. Routability assessments are based on thePROBE approach and an improved construction of underlyingnetlist topologies. Our experimental studies demonstrate theassessment of routability impacts for advanced-node technologyand design options. We demonstrate learning-based Kth prediction to reduce runtime, disk space and commercial tool licensesneeded to implement our framework. Our work enables fasterand more comprehensive evaluation of technology options earlyin the technology development process.Index Terms—VLSI CAD, design-technology co-optimization,machine learning, pathfinding, place-and-route, routability, standard cell, design enablement.WI. I NTRODUCTIONITH the slowdown of pitch scaling in advanced technology nodes, scaling boosters (e.g., buried power railsManuscript received August 2, 2020; revised January 14, 2021; acceptedJune 21, 2021. This work was supported in part by DARPA under GrantHR0011-18-2-0032; in part by NSF under Grant CCF-1564302; in part byQualcomm; in part by Samsung Electronics; in part by NXP Semiconductors;and in part by Mentor Graphics. This article was recommended by AssociateEditor D. Z. Pan. (Corresponding author: Minsoo Kim.)Chung-Kuan Cheng is with the Department of Computer Science andEngineering, University of California at San Diego, San Diego, La Jolla, CA,92093 USA.Andrew B. Kahng is with the Departments of Computer Science andEngineering, and of Electrical and Computer Engineering, University ofCalifornia at San Diego, La Jolla, CA, 92093 USA.Hayoung Kim is with Samsung Electronics Co., Ltd., Hwaseong-si,Gyeonggi-do, South Korea.Minsoo Kim, Daeyeal Lee, Dongwon Park and Mingyu Woo are with theDepartment of Electrical and Computer Engineering, University of Californiaat San Diego, La Jolla, CA, 92093 USA (e-mail: [email protected]).Fig. 1: Three main stages of design-technology co-optimization (DTCO).Today, the design feedback loop takes several weeks to months.(BPR) [33], backside power delivery networks (PDN) [4] andsupervias [14]) have become critical to improve power, performance, area and cost (PPAC) in future technologies. However,scaling boosters have complex impacts on cell architecture,design rules, and other aspects of the design enablement.Thus, holistic optimizations between process technology andchip design are required. Design-technology co-optimization(DTCO) has therefore emerged as the key methodology todecide which scaling boosters enter mass production.DTCO has three main stages: technology, design enablement, and design. As shown in Fig. 1, the technology stageincludes modeling and simulation methodologies related toprocess and device technology; these span technology CAD(TCAD), optical proximity correction (OPC), design rulesand SPICE models. The design enablement stage includesother required inputs to the design process, such as standardcell libraries, IPs and signoff environments. Last, the designstage covers front-end design, logic synthesis, place-and-route(P&R), parasitic extraction, static timing analysis and physicalverifications (design rule check, layout vs. schematic check).For purposes of this paper, technology and design enablementtogether enable the IC design process. Thus, in the remainderof our discussion we use “technology” to encompass theunion of the technology and the design enablement stages,and “design” to refer to the design stage.The key challenge in today’s DTCO is that weeks or monthsare needed for feedback from design back to technology.This is due to the effort and latency of creating prototypedesign enablements and performing design experiments. Ourcontribution lies in automating and greatly speeding up thisfeedback loop, enabling assessment of hundreds of technology

2options within days.Density is the overarching metric for enablement of systemlevel benefits through scaling [40], and directly determines theArea and Cost aspects of PPAC. In our work, we focus onroutability implications of technology choices, since routability and density are intimately tied together. The challenge ofroutability arises as back-end-of-line (BEOL, i.e., metal layers)technology fails to scale down in step with front-end-of-line(FEOL, i.e., device layers). Also, cell heights of standardcell architectures are a crucial lever for density scaling [35],but small standard-cell heights challenge area routing andpin accessibility. Furthermore, high BEOL resistances requiredenser power delivery networks (PDN), which occupy morerouting resources and harm routability.Contributions of This Work. The goal of our work is toenable faster and more comprehensive evaluation of technology options, early in the technology development process. Inparticular, we describe a framework for systematic assessmentof routability across the combined space of technology optionsand design enablement options.Many measures of routability have been developed andapplied over the past decades. These span the use of congestionmaps, metrics of pin accessibility, machine learning-basedcongestion predictors, and other techniques, as we review inSection II below. However, these previous methods to assessroutability do not solve two root causes of the long feedbackloop in DTCO (Fig. 1). The first root cause is that efficientsimultaneous exploration of technology and design options inDTCO is blocked by the effort and expense of the designenablement stage. Producing layouts and characterizationsfor standard-cell libraries requires an enormous amount ofengineering cost and time, due to complex constraints such astransistor-level placement, in-cell routing, and pin accessibility. Today’s DTCO relies on limited, heuristic layout synthesis(e.g., manual layout of 15-60 key cells) to assess a given set oftechnology options. The second root cause is that routabilityassessment methods have mostly focused on assessing designimplementations (e.g., to predict routability of the placement ofa particular netlist), rather than assessing design enablements.Our present work attacks both of the above-mentionedroot causes of long design feedback loops in DTCO. To dothis, we build on two threads of recent works: (1) automaticstandard-cell layout generation using Satisfiability ModuloTheory solvers [8][25], and (2) intrinsic routability assessmentof BEOL stack options via the Kth metric [20]. We reviewthese works in Section II. Our framework is able to provideassessments of intrinsic routability across a range of technology and design parameters reflecting sub-7nm technologies.Our main contributions are summarized as follows. We describe a systematic and complete framework toevaluate routability across key parameters of technologyand design. Our framework is generalizable and flexible;it enables rapid evaluation of hundreds of technology anddesign enablement options within hours or days, providing a valuable tool for early technology development. We propose a pin shape selection strategy based onthe remaining pin access (RPA) [34], along with a topmetal-only pin shape selection strategy, at our designenablement stage. We also extend methods of [8][25]to automatically produce more realistic standard-cell libraries (LEF format [49]) in terms of power and groundpins, contacted poly pitches (CPP) and metal pitches. We extend the method of [20] to assess routability acrossconfigurations of technology and design, rather thanonly BEOL stack options. We study both cell-level anddesign-level routability, and show advantages of usingknight’s tour-based artificial netlist topology generationin cell-level routability assessment. (A knight’s tour is asequence of knight’s moves in a chessboard that visitseach square exactly once. Section IV-A below explainsits use in our methodology.) We achieve seamless integrations with commercial P&Rtooling, via automated generation of power-groundhookups in cell layouts, and routing technology files toreflect modified design rules. We demonstrate accurate learning-based Kth predictionthat reduces runtime, disk storage and tool license overheads of our framework.Our paper is organized as follows. Section II reviewsrelated previous works. Section III gives an overview of ourframework, along with the parameterizations and other detailsof how we generate standard-cell layouts and design enablements. Section IV describes our methodologies for routabilityassessments and learning-based Kth prediction. Section Vshows our experimental setup, key experiments and results. Wegive conclusions and directions of future work in Section VI.II. R ELATED W ORKWe now review relevant previous works. Broadly, thesecan be categorized into works on (1) standard-cell layoutgeneration and (2) routability assessment. Our review includesthe works of [8][25] and of [20] which have provided a basisfor our present work.A. Standard-Cell Layout GenerationAutomatic Standard-Cell Layout Generation. Standard-celllayout synthesis can help library design teams explore cellarchitectures with holistic consideration of transistor placement, in-cell routing, complicated design rules, and pin accessibility. The methods of [15][43] provide co-optimization oftransistor placement and in-cell routing, but do not considersuch aspects as multi-patterning design rules that are seen inadvanced technology nodes. [9][19][26] propose standard-celllayout automation frameworks for sub-7nm technologies, butthese works incorporate multiple heuristic approaches withno guarantees of optimality. Park et al. [25] unify transistorlevel placement and routing with dynamic pin allocation, andapply a satisfiability modulo theories (SMT) solver to achieveoptimal layout solutions.Pin Accessibility-Aware Standard-Cell Layout. One of themost difficult design features for standard-cell layout generation is the pin accessibility, which is challenged by the limitednumber of tracks and complicated design rules. The worksof [32][42] define metrics for pin accessibility within theirobjectives for standard-cell layout optimization. Seo et al. [34]propose the remaining pin access (RPA) metric to capture pinaccess interference from access points of neighboring pins.

3Cheng et al. [8] devise “at-least-k” Boolean constraints thatguarantee a minimum number of pin openings (access points)per pin in the cell layout.The SMT-based Standard-Cell Layout Generation of[8][25]. Our present work builds on the SMT-based parametricstandard-cell generation framework of [8][25]. This frameworktakes in three main inputs. (1) Cell architectures: number ofrouting tracks and transistor fins, and track pitches. (2) Netlist:component connectivity of library cell. (3) Design rules:parametric conditional design rules depending on cell architecture. Given these inputs, a cell layout is produced that isoptimal with respect to cell area, M2 track use (routability) androuted metal length, in lexicographic order of these criteria.A unifying dynamic pin allocation (DPA) constraint integratesadditional design constraints such as transistor placement, incell routing, conditional design rules and pin accessibilityconstraints. This yields a constraint satisfaction formulationthat produces an optimized cell layout via a single multiobjective optimization.We observe that these previous works do not provide necessary enablements of commercial standard-cell P&R, such asLEF [49] generation, PDN generation, and routing technologyfile generation. Nor do these works support control parametersfor standard-cell layout generation that are relevant in sub7nm nodes. We describe a complete framework to supportboth standard-cell layout generation and associated P&R enablement. Our layout generation uses RPA-based and topmetal-only pin shape selections to improve pin accessibility.B. Routability AssessmentRoutability is a hard constraint in the modern (fixed-die) placeand-route context. Thus, many previous works have studied routability-driven placement, as well as ripup-and-reroutemethods in global routing. For example, [7][18][22][27] allpropose routability-driven placement based on congestionmaps derived from early trial or global routing. Pin accessibility of a given standard-cell instance also affects routability.The above-mentioned work of [34] describes pin accessibilityaware detailed placement based on the RPA metric. However,we do not focus on placement and routing optimizations, butrather on methods for assessment of routability.Routability Analysis and Prediction. Tseng et al. [38]propose a systematic framework with P&R tools to checkroutability, aiming to improve placement outcomes. The authors propose standard cell-level and placement-level routability scores to generate cell spacing constraints. [17] proposean optimal ILP-based detailed router and evaluate feasibility(routability) of routing clips based on an ILP solver. Theauthors of [21][29][30] use Boolean satisfiability (SAT) toanalyze routability under conditional design rules. [29][30]furthermore extract minimal unsatisfiable subsets to diagnosebottlenecks when designs are proven to be unroutable.Several recent works propose machine learning (ML)based routability predictions. Zhuo et al. [44] propose a newroutability prediction model based on supervised learning inplacement. The works of [6][41] predict routability based onconvolutional neural networks (CNN) and support vector machines (SVM), respectively. Chan et al. [2] also propose SVM-based routability prediction, but aim to evaluate routability forvarious BEOL stack options.The PROBE Routability Measurement Utility of [20]. Ourpresent work builds on the “PROBE” framework of [20],which gives a measure of inherent routability of BEOL stackoptions. PROBE begins with a placement solution that iseasy to route – e.g., a regular mesh placement of a meshnetlist topology. PROBE then iteratively swaps the locationsof random pairs of neighboring placed cells, progressively“tangling” the placed netlist until the routing fails with morethan some threshold number of post-route DRC violations. Thenumber of random neighbor cell swaps performed, normalizedto the number of instances in a design, is denoted by K. Thenumber of swaps beyond which routing fails is denoted asthe K threshold (Kth ), and captures intrinsic routing capacity(e.g., of a given BEOL stack).Fig. 2(a) shows the scope of PROBE. Given a placement,a set of BEOL stack options {B1 , B2 , ., Bi } can be rankedin terms of routability. The framework supports two types ofplacements, shown in Fig. 3. Mesh-like placements do notreflect any specific design; they consist of an array of instancesof a given 2-input or 3-input cell. Connections are madebetween neighbors, inducing a near-meshlike netlist topology.Cell width-regularized placements are design-specific, and areproduced by commercial P&R tools. However, the standardcells in the placements are all given the same cell width toavoid illegal placements after neighbor cell swaps.We observe that [20] is applied only to BEOL stack options,and does not cover the rich space of FEOL technology anddesign enablement options. Moreover, the near-meshlike topology can produce only a limited range of routed wirelength andRent parameter values that may not match realistic values. Theframework we describe below supports DTCO with routabilityassessment across technology and design enablement options.We use a knight’s tour-based construction that can better reflectactual design attributes.III. T HE PROBE2.0 F RAMEWORKOur PROBE2.0 framework is shown in Fig. 2(b). It takestechnology and design parameters as primary inputs, andconsists of three major stages. (1) The standard-cell layoutgeneration stage is based on input technology parameters, andis performed using an extension of an SMT-based standardcell layout generation [8][25]. It produces purely grid-basedpin locations and cell boundaries. (2) The design enablementstage begins with the generated standard-cell layouts, and isalso performed according to the input technology parameters.Design enablement generates LEF [49], Liberty [50] androuting technology files. LEF file generation converts theprimitive form of layouts to LEF format. The conversion considers real-world constraints for the stability of standard-cellcharacteristics, as detailed in Section III-D. (3) The routabilityassessment stage uses a knight’s tour-based topology as wellas open-source designs with the PROBE approach [20]. Also,Fig. 2(c) shows how the PROBE2.0 flow can be realizedwith learning-based Kth prediction, where a trained machinelearning model enables more efficient routability assessment.

4Fig. 2: Overall flows for PROBE [20] and PROBE2.0. (a) PROBE evaluates BEOL stack options (Bi ) by performing neighboring cell swaps until routing failsat a (normalized) number of swaps Kth . (b) The PROBE2.0 flow, including standard-cell layout generation [8][25], automated design enablement generation,and routability assessment with multiple P&R runs. (c) A PROBE2.0 flow using a trained learning-based model to predict Kth .Fig. 3: Placements for PROBE [20]; (a) A mesh-like placement based ona 2-input cell. The red arrows show connections between neighbor instances, inducing a near-meshlike netlist topology. (b) A cell width-regularizedplacement. The orange-striped cells are considered to be neighbors of theblue-striped cell. The blue-striped cell is swapped with a randomly-selectedneighbor.Fig. 4: A grid-based standard-cell architecture and technology parameters forstandard cells.The remainder of this section describes aspects of standardcell architecture, technology and design parameters, and design enablement in our framework. Our routability assessmentand learning-based Kth prediction are explained in Section IV.A. Standard-Cell ArchitectureFig. 4 shows a grid-based standard-cell architecture andtechnology parameters of standard cells, as used in our work.We follow the 7nm standard-cell architectures in [10][39] togenerate the grid-based P&R graph with four layers T S/P C,M 0, M 1, and M 2 as depicted in Fig. 5. T S/P C and M 0layers are included in FEOL layers and M1 and M2 layers areincluded in BEOL layers. Next, we give detailed definitionsof the eight technology parameters and five design parametersthat PROBE2.0 supports as user inputs.B. Definitions of Technology ParametersTechnology parameters include various options for processtechnology as well as design enablement.(1) Fin: The number of fins for devices of standard cells. Weuse 2 and 3 for Fin [10][39].(2) CPP: Contacted poly pitch for standard cells. We use 48and 54nm for CPP [35][39].(3) MP: Metal pitch for M2 and M3 routing layers. We use24, 32 and 40nm for MP [35][39].(4) RT: The number of available M2 routing tracks for standardcells. We use 4, 5 and 6 for RT [10][39].Fig. 5: Schematic view of a 7nm layout [10]. Rx denotes diffusion areas.Fins are colored in yellow. M0 and M2 are horizontal while PC (Gate), TS(Source/Drain), and M1 are vertical layers. CA, V0 and V1 are vias.(5) PGpin: Pin types for power and ground of standard cells.We support three types of power and ground pins: M1 [39],M1 M2 [3], and BPR [33]. M1 denotes power and ground pinson the M1 layer. M1 M2 denotes power and ground pins onboth M1 and M2 layers. BPR has no power and ground pinson BEOL layers. M1 and M2 power and ground pins havewidth equal to twice the minimum width on Mx (M1, M2and M3) layers. (Thus, since minimum width and minimumspacing are each equal to half the metal pitch MP, the powerand ground pins have widths equal to the Mx pitch.) Also, inenablement of BPR, the width of M1 power pins is the sameas the minimum width of Mx. This is because commercialP&R tools require power and ground pins to be connected toPDN. Note that the M1 power and ground pins do not affectroutability since the minimum routing layer is M2.(6) CH: Cell height of standard cells, expressed as a number ofM2 routing track (T) pitches. For example, if M2 routing trackpitch is 40nm and the cell height is 240nm, then CH is 6. We

5use and refer to standard cells with 5T, 6T, 7T and 8T [10][39]cell heights. Note that CH depends on the combination of RTand PGpin. For example, if RT is 4 and PGpin is M1, thenCH is 6. If RT is 4 and PGpin is BPR, then CH is 5.(7) MPO: The number of minimum pin openings (accesspoints) per pin. For example, if MPO is 2, every pin musthave at least two access points for the generated standard-celllayout. We use the values of 2 and 3 for MPO [8][25].(8) DR: Design rule sets. In this work, all design rules aredefined based on grids. We assume that our technologies arebased on Extreme Ultraviolet (EUV) lithography. We definethree fundamental grid-based design rules for Mx layers, DRMAR, DR-EOL and DR-VR [8][25]; we also define two designrule sets, namely, EUV-Loose (EL) and EUV-Tight (ET).Fig. 6 illustrates the three design rules. (i) DR-MAR denotesminimum area rules, as shown in Fig. 6(a). When a metalshape occupies only one grid point and DR-MAR is 1, thisviolates the DR-MAR rule. I.e., a metal shape must be longenough to occupy at least two routing grid points. (ii) DREOL denotes end-of-line rules, as shown in Fig. 6(b) and (c).When edges of two co-linear metal shapes are placed nextto each other and DR-EOL is 1, this violates the DR-EOLrule. I.e., there must be at least one unoccupied routing gridpoint between edges of metal shapes. When DR-EOL is 2,there must be at least two empty routing grid points. (iii) DRVR denotes via restriction rules, as shown in Fig. 6(d). Thefigure shows the prohibited locations for other vias, relativeto the placement of a given via. When DR-VR is 1, only fourneighbors are blocked by the DR-VR rule.Our two design rule sets each comprise combinations ofspecific design rule settings, as follows. EL consists of DRMAR 1, DR-EOL 1, and DR-VR 1. ET consists ofDR-MAR 1, DR-EOL 2, and DR-VR 1.Last, we note that in this work, we assume metal enclosuresof vias are 10nm in a preferred direction and 0nm in anon-preferred direction. Also, many practical design rules canbe framed using our grid-based design rules. For example,rules for end-to-end spacing and minimum enclosures can becaptured with the DR-EOL rule. We note that a wide rangeof via rules, including center, edge and corner spacing rules,can be captured with the DR-VR rule.Fig. 6: DR-MAR, DR-EOL, and DR-VR design rules.Based on the cell architecture of Fig. 4 and the abovetechnology parameters, our standard-cell layout generation cangenerate layouts for various cell architectures. In particular,our studies use six types of cell architectures with the combinations of Fin, RT and PGpin and CH shown in Table I.TABLE I: Standard-cell architectures in our experiments.FinRT243536PGpinM1/M1 M2BPRM1/M1 M2BPRM1/M1 M2BPRCH566778C. Definitions of Design ParametersOur framework uses the following design parameters.(1) BEOL: Metal stack options. We define 9M, 10M, 11Mand 13M BEOL stack options based on scaling down froma commercial 14nm technology. Recall that Mx (1X layer)pitch, i.e., MP above, is a technology parameter that we canvary in routability exploration. To scale down a 14nm BEOLtechnology to sub-7nm technologies, we define 2X, 3.2X, 9Xand 18X layer pitches based on 40nm as the 1X pitch; thisreflects advanced-node stacks as well as considerations suchas litho/cost “cliff” ( 80nm pitch limit for single-exposure193i patterning). We calculate the routing resource of [20]forPeach BEOL stack option. The routing resource is definedas b (1/pitchb ) where b denotes a metal layer and pitchb isthe pitch of b. Essentially, this sums available routing tracksover all routing layers. Table II summarizes layer counts perpitch and routing resource (R) for the BEOL stack options.(2) PDN: Power delivery network options. These include traditional PDN with different layers and pitch, and backside PDNas a scaling booster for advanced technology. We define fourPDN options: Backside, Sparse, Middle and Dense. Table IIIshows the detailed information of these PDN options.(3) Tool: Commercial P&R tools [46][55], referred to only asTool A and Tool B to comply with vendor license agreements.(4) Util: Placement utilization (0.6, 0.7, 0.8).(5) Design: Designs studied in routability assessment. Weuse knight’s tour-induced artificial topologies, along with fouropen-source designs (AES, LDPC, JPEG, VGA) from OpenCores [51]. The respective instance counts of AES, LDPC,JPEG and VGA are approximately 13K, 56K, 69K and 72K.Table IV summarizes the technology and design parametersthat we use in our experiments. Note that in our framework,the parameter list is flexible and readily extendable. Thisenables accommodation of new technology requirements ornew scaling booster options. For example, sets of smaller CPPand MP values, including with non-unit “gear ratio” valuessuch as 2:1 or 3:2 (e.g., CPP relative to vertical M1 pitch),can be evaluated with the PROBE2.0 framework. This serves areal DTCO and technology pathfinding problem in industry forsub-3nm technologies, through the end of the lateral scalingroadmap. Also, we can easily add new designs and/or PDNstrategies as design parameters, for richer assessments.TABLE II: Four BEOL stack options. R denotes routing ANA218X2122R104.4117.8120.1116.3

6TABLE III: Details of PDN options. All numbers are pitches in units ofµm for each layer. “P” indicates that we use a given layer only for PDNat maximum area density, and do not allow the layer to be used for signalrouting. The width of M5 stripes is 0.96µm and the width of M6/M8 stripesis 1.296µm. The spacing between VDD and VSS stripes on 2X and 3.2Xlayers is 0.550µm. Backside PDN does not use any BEOL layers for M12M13M5M8M12M131010PP2020PP4040PPTABLE IV: Technology and design parameters in our TPGpinCHMPODRBEOLPDNToolUtilDesignOption2, 354, 4824, 32, 404, 5, 6BPR, M1, M1 M25, 6, 7, 82, 3EUV-Loose, EUV-Tight9M, 10M, 11M, 13MBackside, Sparse, Middle, DenseTool A, Tool B0.6, 0.7, 0.8A knight’s tour, AES, LDPC, JPEG, VGAD. Design EnablementOur design enablement produces ready-to-use standard libraries and required inputs for P&R. We generate LEF formatfrom the primitive layout produced by SMT-based cell layoutgeneration. Layouts are fully grid-based, with CPP and MPtechnology parameters defining the grid pitches. Importantly,we propose two pin shape selection schemes: RPA-based pinshape selection and top-metal only pin shape selection.RPA-Based Pin Shape Selection. The SMT-generated celllayouts can have multiple distinct pin shapes for a single pin. Access to such pins must be carefully handled toavoid instability of timing and power models of the standardcells. Fig. 7(a) shows the initial SMT-generated layout of anOAI21 X1 cell. In the figure, pin ZN has two M1 shapes,ZNa and ZNb . When connections are made to different pinshapes (i.e., ZNa or ZNb ), at least one of the cases will notmatch the cell’s characterized timing and power model. Forexample, when output pin ZN is connected through the M1pin shape ZNa , the cell delay is 10ps, but when the connectionis made through ZNb , the cell delay is 8ps. This instabilitywith respect to the cell timing/power model is unacceptablein modern design enablements. Therefore, when a pin hasmultiple candidate shapes, our framework chooses one of theseshapes to use in the standard-cell layout that is produced.Given our focus on routability, we apply pin shape selectionbased on the Remaining Pin Access (RPA) pin accessibilitymetric [34]. Fig. 7 shows an example of our pin shapeselection. Accessibility of a given pin is affected by other pinswithin a distance dint . We set dint as 1.0 for the EL designrule set, and 2.0 for the ET design rule set. We then calculateRP A values for each pin shape. From [34], pin access 0BA2ZN(a)A1OBS(b)Fig. 7: Example of pin shape selection in a standard cell, with Fin 2, RT 5, MPO 2, and the EL design rule set. (a) Initial layout of OAI21 X1 fromSMT-based layout generation, with calculated RPA values of 2.0, 0.83, 1.0,1.0 and 1.5 for ZNa , A1, A2, ZNb and B respectively. (b) The OAI21 X1layout after RPA-based pin shape selection. The ZNa pin shape becomes theonly pin shape for ZN , and ZNb become

Section V shows our experimental setup, key experiments and results. We give conclusions and directions of future work in Section VI. II. RELATED WORK We now review relevant previous works. Broadly, these can be categorized into works on (1) standard-cell layout generation and (2) routability assessment. Our review includes